1. Field of the Invention
This invention relates to a method for fabricating a semiconductor device and more particularly to a method for forming an electrode structure in an IC device.
2. Description of the Prior Art
Silicides for IC applications are described by T. Hirao et al. in Extended Abstracts of the 17th Conference on Solid State Devices and Materials, Tokyo, 1985, pp. 381-384 and also by S. P. Murarka in SILICIDES FOR VLSI APPLICATIONS, pp. 66-69, 1983, Academic Press.
FIGS. 1A to 1E are enlarged fragmentary sectional views illustrating the principal steps in a conventional method for forming a silicide electrode in a semiconductor device.
Referring to FIG. 1A, an oxide layer 2 is formed on, e.g., a p-type silicon substrate 1 and then coated with a passivation film 3 of phospho-silicate glass (PSG).
Referring to FIG. 1B, when an n.sup.+ -type region 41 to be brought into contact with an electrode is formed at a part on the p-type silicon substrate 1, a contact hole 40 is opened through both the PSG film 3 and the oxide layer 2, followed by ion implantation of n-type impurity through the hole 40.
Referring to FIG. 1C, the surface of the above processed substance is then covered with a metal film 5 of Ti, Mo, W, Pt, Pd or the like. The metal film 5 is then silicidized in a self-aligned manner by annealing only in an area where it is in direct contact with the n.sup.+ -type region 41 of the silicon substrate 1.
Referring to FIG. 1D, the remaining metal film regions which have not been silicidized are then removed by aqua regia. As a result, a metal silicide electrode 51 is formed on the n.sup.+ -type region 41.
Finally referring to FIG. 1E, a lead wire 6 of a low resistive metal such as aluminum (A1) is formed over the silicide electrode 51. The silicide electrode prevents junction-spike (for example, preventing reaction between the A1 wire and the silicon substrate).
However, when it is desired for high integration and high performance of a device that a plurality of electrode contact areas are formed close to one another on a semiconductor substrate, the conventional method illustrated in FIGS. 1A to 1E arouses the following problem.
FIG. 2 is a sectional view of an electrode structure formed by the conventional method. A first n.sup.+ -type layer 41 and a second n.sup.+ -type layer 42 are formed to be close to each other on a semiconductor substrate 1. A first A1 wire 61 is formed over a first silicide electrode 51 which is in direct contact with the first n.sup.+ -type layer 41, and similarly, a second A1 wire 62 is formed over a second silicide electrode 52 which is in direct contact with the second n.sup.+ -type layer 42. In this structure, the separation D between the contact holes must be larger than the separation A between the wires 61, 62 plus a total width of margins B and C of the respective wires 61, 62 extending beyond the respective contact holes, and such margins remain inevitably even if the distance A is reduced by improvement in accuracy of photoetching. Therefore, the minimum separation E between the neighboring n.sup.+ -type regions 41, 42 is limited depending on the minimum separation A between the wires 61, 62. To resolve this problem, the following electrode structure may be considered.
FIG. 3 is a sectional view of another electrode structure similar to that of FIG. 2, except that a first n.sup.+ -type region 41 is extended to approach a second n.sup.+ -type region 42. Although the separation between the n.sup.+ -type regions 41, 42 can be surely reduced independently on the minimum separation between the wires 61, 62 in this structure, at least one of the n.sup.+ -type regions 41, 42 is necessarily formed large in area, so that the device characteristics will be deteriorated due to an increase in the junction capacitance.